1. Field of the Invention
The present invention relates to a method for driving a self-scanning light-emitting element array, particularly to a method for driving a self-scanning light-emitting element array in which an effect to an image is not caused even if there is a thyristor which is not lighted in a light-emitting portion due to the breakage of a current supply line for thyristors in the light-emitting portion.
2. Related Art
A light-emitting element array in which a plurality of light-emitting elements are integrated on the same substrate is utilized as an optical writing head for an optical printer and the like with combining it to a driving IC. The inventors of the present invention have interested in a three-terminal light-emitting thyristor having a pnpn-structure as a component of the self-scanning light-emitting element array, and have already filed several patent applications (see Japanese Patent Publication Nos. 1-238962, 2-14584, 2-92650, and 2-92651) showing that a self-scanning operation for the thyristors in a light-emitting portion may be realized. These publications have disclosed that such a self-scanning light-emitting element array has a simple and compact structure for a light source of a printer, and has smaller arranging pitch of light-emitting elements.
The inventors have further provided a self-scanning light-emitting device having such structure that a transfer portion including switch elements (light-emitting thyristors) array is separated from a light-emitting portion including light-emitting elements (light-emitting thyristors) array (see Japanese Patent Publication No. 2-263668).
Referring to FIG. 1A, there is shown an equivalent circuit diagram of a self-scanning light emitting array in which a transfer portion and light-emitting portion are separated. The self-scanning light-emitting element array comprises a transfer portion including thyristors S1, S2, S3 . . . and a light-emitting portion including thyristors L2, L2, L3 . . . . The structure of the transfer portion utilizes a diode-coupling system, i.e., the neighbored gates of the thyristors S1, S2, S3 . . . are connected by diodes D1, D2, D3 . . . , respectively. A power Supply VGA is connected to gate g1, g2, g3 . . . in the transfer portion through gate load resistors Rg1, Rg2, Rg3, respectively. Respective gates g1, g2, g3 . . . of the thyristors S1, S2, S3 . . . are also connected corresponding gates g′1, g′2, g′3 of the thyristors L1, L2, L3 in the light-emitting portion through resistors Rp1, Rp2, Rp3 . . . . Respective cathodes of the thyristors in the transfer portion are connected alternately to φ1 line 12 and φ2 line 14.
Current limiting resistors R1 and R2 are inserted in the φ1 line 12 and φ2 line 14, respectively.
Respective cathodes of the thyristors L1, L2, L3 . . . in the light-emitting portion are connected to a light-emitting signal φI line 16. A current limiting resistor RI is inserted in the φI line 16.
By driving the self-scanning light-emitting element array thus structured, a thyristor in the light emitting portion designated by the turned-on state of a thyristor in the transfer portion driven by two-phase clock pulses φ1 and φ2 is lighted or lighted out to make an image.
In FIG. 1B, there shown High/Low-level of the clock pulses φ1, φ2 and the light-emitting signal φI, turned-on/turned-off state of the thyristors in the transfer portion, and lighted/lighted out state of the thyristors in the light-emitting portion. As shown in FIG. 1B, a time period during which both clock pulses φ1 and φ2 are at Low-level is shown by ta(=t3−t2), a time period until when the light-emitting signal φI becomes Low-level after any of clock pulses φ1 and φ2 becomes High-level is shown by tb(=t4−t3), and a transfer period is shown by T(=t5−t2). Herein, a time when the light-emitting signal φI becomes High-level is set equally to a time when next clock pulse becomes Low-level to increase a light-emitting period. As a result, the light-emitting time period is equal to (T−ta−tb).
As an example, a transfer period T=t5−t2=500 ns, a time period ta=t3−t2=20 ns, and a time period tb=t4−t3=20 ns.
As a line for supplying a current to the thyristors in the light-emitting portion is thin in its width and the density of a current through it is large, there is a possibility of the breakage of the line due to an electro-migration. In a conventional drive method, the transfer operation becomes unstable when the breakage of a line is caused, and the thyristors succeeding the breakage point in a transfer direction in the light-emitting portion may not be lighted. In such a case, an image defect will be caused in which a part of an image is not printed across several mili meters in width (i.e., white stripe) for the worst case, which depends on the breakage point. This defect will be remarkable in a printed image. As a color printer having a printing density of 1200 dpi (dots per inch) for A3 size comprises a print head including 60,000 thyristors in the light emitting portion, a serious image defect will be caused even if only one current supply line for the thyristors in a light-emitting portion is broken. Therefore, a high reliability is required for respective thyristors in the light-emitting portion, resulting in a cost up of a print head.
The reason why an abnormal transfer operation is caused will now be described hereinafter. As shown in FIG. 2A, it is assumed that a cathode line for the thyristor L5 in a light-emitting portion is broken. FIG. 2B shows High/Low-level of the clock pulses φ1, φ2 and the light-emitting signal φI, turned-on/turned-off state of the thyristors in the transfer portion, and lighted/lighted out state of the thyristors in the light-emitting portion.
As shown in FIG. 2B, it is assumed that when the clock pulse φ1 is at High-level, the clock pulse φ2 is at Low-level, and the light-emitting signal φI Low-level at the time t1, the thyristor S4 in the transfer portion is turned on, and the thyristor L4 in the light-emitting portion is lighted. At the time t2, the clock pulse φ1 becomes Low-level, and the light-emitting signal φI High-level, so that the thyristor S5 is turned on, and the thyristor L4 is lighted out. Subsequently, at the time t3, the clock pulse φ2 becomes High-level, and the thyristor S4 is turned off. Subsequently, while the light-emitting signal φI becomes Low-level at the time t4, the thyristor L5 connected to the turned-on thyristor S5 may not be lighted due to the breakage of the line. At this time, one thyristor among the thyristors L1-L6 in the light-emitting portion connected to the φI line 16 is turned on, the gate voltage of the one thyristor having the highest voltage among the gate voltages on the gates g′1−g′6.
FIG. 3 shows the variation of voltages of the gates g4, g6, g′4, g′6 after the time t2. While the light-emitting signal φI becomes High-level at the time t2 to light out the thyristor L4, the voltages of the gate g′4 as well as the gate g4 becomes approximately 0 volts because the clock pulse φ2 is still at Low-level. When the clock pulse φ2 becomes High-level at the time t3, the thyristor S4 is also turned off and then the gates g4 and g′4 are pulled down through the resistors Rg4 and Rp4, so that respective voltages of the gates g4 and g′4 are decreased at the time constants τg and τ′g toward the voltage VGA (−5 volts). In FIG. 3, the voltages of the gates g4 and g′4 at the time t4 are designated by g4 (t4) and g′4 (t4), respectively. At this time, the resistance of the gate g′4 is larger than that of the gate g4, so that the time constant τ′g becomes larger to cause the rate of voltage decreasing to be slow.
On the other hand, the thyristor S5 is turned on at the time t2, so that respective voltages of the gates g6 and g′6 become approximately −VD (VD is a forward rising voltage of the coupling diode D). Subsequently, when the light-emitting signal φI becomes Low-level at the time t4, respective voltages of the gates g′4, g′5 and g′6 become as follows:                the voltage of the gate g′4=g′4(t4)        the voltage of the gate g′5=about 0 volts        the voltage of the gate g′6=g′6(t4).As the voltage of the gate g′5 is highest, the thyristor L5 will be lighted in a normal case. However, the thyristor L5 may not be lighted because the cathode line for the thyristor L5 is broken. In this case, the thyristor having the higher voltage between the gate voltage g′4(t4) and g′6(t4) is lighted. As g′4(t4)>g′6(t4) in FIG. 3, the thyristor L4 is lighted again. At this time, the thyristor S5 is turned on in the transfer portion and the thyristor L4 is lighted in the light-emitting portion, which is an unstable state.        
Subsequently, the clock pulse φ2 becomes Low-level at the time t5. In a normal state, the gate voltage g6 (t5) is approximately −VD which is the highest gate voltage among the thyristors connected to the clock pulse φ2 line 14. However, the thyristor L4 is lighted, so that the voltage of the gate g4 is a voltage divided by the resistors Rp4 and Rg4. In the case of Rp4=5 kΩ, Rg4=20 kΩ for example, the voltage g4 (t5) is approximately −1 volts. As a result, the light-emitting φI signal becomes High-level, and then g4(t5)>g6(t5) at the time t5 when the thyristor L4 is lighted out. Consequently, the thyristor S4 is turned on as shown in FIG. 3B. When the light-emitting signal φI becomes Low-level at the time t7, the thyristor L4 is lighted again. The situation described above is repeated hereinafter, so that the thyristor L4 is lighted repeatedly and the thyristors after the thyristor L5 in the light-emitting portion are not lighted. The transfer operation of the thyristors in the light-emitting portion is stopped, resulting in the defect of white stripe in printing.